During front end-of-the-line processing, a plurality of semiconductor devices (e.g., transistors, resistors, and the like) are formed on a semiconductor wafer. During back end-of-the-line (BEOL) processing, a plurality of semiconductor devices are interconnected to form a plurality of integrated circuits on the wafer, which are subsequently separated into individual die during wafer dicing. Interconnection of the semiconductor devices is accomplished via the formation of a plurality of BEOL layers, which include, in part, a number of metallization layers and a number of interlayer dielectric layers (ILD layers).
Capacitors are used in many electrical and electronic devices to implement a wide variety of functions. Capacitors may be fabricated as part of the back-end-of-the-line (BEOL) process. BEOL begins when a first metallization layer is deposited on the semiconductor wafer. Back end capacitors typically require a large amount of chip area and often compete for available chip area in which transistors can be formed.
There is a continual interest in the integration density of semiconductor devices, such as capacitors, etc. on the integrated circuit. High capacitance is desired for capacitors, including DRAM storage capacitors. “Capacitance” refers to the capacity of the device for storing electric charge. One approach to increase the capacitance is to increase the area of the capacitor electrodes. Capacitance is directly proportional to the surface area of the electrodes. However, this approach results in an increase in the actual area occupied by the capacitor on the integrated circuit or an increase in the size of the chip (the integrated circuit). Neither of these options is desirable as increasing the actual area occupied by the capacitor excludes other semiconductor devices and an increase in the chip size undermines the interest toward integration density.
Accordingly, it is desirable to provide integrated circuits having a capacitor with increased capacitance per unit area (i.e., a “place-efficient capacitor”) and methods for fabricating the same. It is also desired to increase the capacitance of the capacitor without occupying more chip space or increasing the size of the integrated circuit to enable an increase in the number of semiconductor devices integrated on a given area of the integrated circuit. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.